Related patent applications:
The invention disclosed herein is related to the U.S. patent application Ser. No. 07/864,112, filed Apr. 6, 1992, now abandoned, entitled "Massively Parallel Array Processor", by G. G. Pechanek, et al., assigned to the IBM Corporation and incorporated herein by reference.
The invention disclosed herein is also related to the co-pending U.S. patent application by G. G. Pechanek, et al. which is entitled "DISTRIBUTED CONTROL PIPELINE WITH JOINT PE/SEQUENCER CONTROL", Ser. No. 08/365,858, filed Dec. 29, 1994, IBM Docket Number RA9-94-041, assigned to the International Business Machines Corporation, and incorporated herein by reference.
The invention disclosed herein is also related to the co-pending U.S. patent application by G. G. Pechanek, et al. which is entitled "ARRAY PROCESSOR TOPOLOGY RECONFIGURATION SYSTEM AND METHOD", Ser. No. 08,366,140, filed Dec. 29, 1994, IBM Docket Number RA9-94-043, assigned to the International Business Machines Corporation, and incorporated herein by reference.
Many signal processors, e.g. ISP-5.6, use instructions which produce multiple independent execution actions to occur per instruction cycle. These "compound-instructions" are typically difficult to encode within a single instruction word since they must specify multiple operations. Consequently, compromises are typically done in architecting the compound instructions, thereby limiting the flexibility and generality in the specification of operands and result destinations. A number of alternatives to providing compound instructions have been proposed. In particular the G. D. Jones, et al., "Selecting Predecoded Instructions with a Surrogate", IBM TDB, Vold. 36, No. 6A, June 1993, p. 35, and G. D. Jones, et al., "Pre-Composed Superscaler Architecture", IBM TDB, Vol. 37, No. 9, September 1994, p. 447. The approach used herein is an extension of the concepts described in these two papers. This invention is primarily concerned with new concepts not covered in either of these earlier works.
In the surrogate concept, a Very Long Instruction Word (VLIW) is created from multiple simplex instructions. Multiple VLIWs can be created and implemented either in Read Only Memory (ROM) or created by a sequence of instructions which are identified to load the surrogate memory. A surrogate simplex instruction is then used to point to a specific VLIW for execution. In the PEs, a VLIW is stored in a surrogate memory made up of multiple instruction slots with each slot associated with a 32-bit execution unit plus slots assigned for Load and Store joint SP/PE instructions.